------------- Begin Cut here for COMPONENT Declaration ------
component edb_top
  port (
         bscan_CAPTURE : in  std_logic;
         bscan_DRCK    : in  std_logic;
         bscan_RESET   : in  std_logic;
         bscan_RUNTEST : in  std_logic;
         bscan_SEL     : in  std_logic;
         bscan_SHIFT   : in  std_logic;
         bscan_TCK     : in  std_logic;
         bscan_TDI     : in  std_logic;
         bscan_TMS     : in  std_logic;
         bscan_UPDATE  : in  std_logic;
         bscan_TDO     : out std_logic;
         LVDS_TX_clk   : in  std_logic;
         LVDS_TX_lvds_tx_data1 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data2 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data3 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data4 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data5 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data6 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data7 : in  std_logic_vector(7 downto 0);
         LVDS_TX_lvds_tx_data8 : in  std_logic_vector(7 downto 0);
         LVDS_RX_clk   : in  std_logic;
         LVDS_RX_lvds_rx_data1 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data2 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data3 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data4 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data5 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data6 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data7 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data8 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip1 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip2 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip3 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip4 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip5 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip6 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip7 : in  std_logic_vector(7 downto 0);
         LVDS_RX_lvds_rx_data_slip8 : in  std_logic_vector(7 downto 0);
         LVDS_RX_stat1 : in  std_logic;
         LVDS_RX_stat2 : in  std_logic;
         LVDS_RX_stat3 : in  std_logic;
         LVDS_RX_stat4 : in  std_logic;
         LVDS_RX_stat5 : in  std_logic;
         LVDS_RX_stat6 : in  std_logic;
         LVDS_RX_stat7 : in  std_logic;
         LVDS_RX_stat8 : in  std_logic;
         vio_ctrl_status_clk : in  std_logic;
         vio_ctrl_status_pll_locked : in  std_logic;
         vio_ctrl_status_rx_heartbeat : in  std_logic;
         vio_ctrl_status_tx_heartbeat : in  std_logic;
         vio_ctrl_status_det_pass : in  std_logic;
         vio_ctrl_status_stat1 : in  std_logic;
         vio_ctrl_status_stat2 : in  std_logic;
         vio_ctrl_status_stat3 : in  std_logic;
         vio_ctrl_status_stat4 : in  std_logic;
         vio_ctrl_status_stat5 : in  std_logic;
         vio_ctrl_status_stat6 : in  std_logic;
         vio_ctrl_status_stat7 : in  std_logic;
         vio_ctrl_status_stat8 : in  std_logic;
         vio_ctrl_status_data_source : out std_logic;
         vio_ctrl_status_lvds_tx_data : out std_logic_vector(7 downto 0);
         vio_ctrl_status_err_clear : out std_logic;
         vio_ctrl_status_bitslip_binding : out std_logic;
         vio_ctrl_status_bitslip_all : out std_logic;
         vio_ctrl_status_bitslip1 : out std_logic;
         vio_ctrl_status_bitslip2 : out std_logic;
         vio_ctrl_status_bitslip3 : out std_logic;
         vio_ctrl_status_bitslip4 : out std_logic;
         vio_ctrl_status_bitslip5 : out std_logic;
         vio_ctrl_status_bitslip6 : out std_logic;
         vio_ctrl_status_bitslip7 : out std_logic;
         vio_ctrl_status_bitslip8 : out std_logic;
         vio_tx_data_clk : in  std_logic;
         vio_tx_data_lvds_tx_data1 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data2 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data3 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data4 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data5 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data6 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data7 : in  std_logic_vector(7 downto 0);
         vio_tx_data_lvds_tx_data8 : in  std_logic_vector(7 downto 0);
         vio_rx_data_clk : in  std_logic;
         vio_rx_data_lvds_rx_data1 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data2 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data3 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data4 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data5 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data6 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data7 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data8 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip1 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip2 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip3 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip4 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip5 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip6 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip7 : in  std_logic_vector(7 downto 0);
         vio_rx_data_lvds_rx_data_slip8 : in  std_logic_vector(7 downto 0);
         vio_rx_data_err_sum1 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum2 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum3 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum4 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum5 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum6 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum7 : in  std_logic_vector(14 downto 0);
         vio_rx_data_err_sum8 : in  std_logic_vector(14 downto 0)
       );
end component ;
---------------------- End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template -----
edb_top_inst : edb_top
port map (
           bscan_CAPTURE => jtag_inst1_CAPTURE,
           bscan_DRCK    => jtag_inst1_DRCK,
           bscan_RESET   => jtag_inst1_RESET,
           bscan_RUNTEST => jtag_inst1_RUNTEST,
           bscan_SEL     => jtag_inst1_SEL,
           bscan_SHIFT   => jtag_inst1_SHIFT,
           bscan_TCK     => jtag_inst1_TCK,
           bscan_TDI     => jtag_inst1_TDI,
           bscan_TMS     => jtag_inst1_TMS,
           bscan_UPDATE  => jtag_inst1_UPDATE,
           bscan_TDO     => jtag_inst1_TDO,
           LVDS_TX_clk      => #INSERT_YOUR_CLOCK_NAME,
           LVDS_TX_lvds_tx_data1    => LVDS_TX_lvds_tx_data1,
           LVDS_TX_lvds_tx_data2    => LVDS_TX_lvds_tx_data2,
           LVDS_TX_lvds_tx_data3    => LVDS_TX_lvds_tx_data3,
           LVDS_TX_lvds_tx_data4    => LVDS_TX_lvds_tx_data4,
           LVDS_TX_lvds_tx_data5    => LVDS_TX_lvds_tx_data5,
           LVDS_TX_lvds_tx_data6    => LVDS_TX_lvds_tx_data6,
           LVDS_TX_lvds_tx_data7    => LVDS_TX_lvds_tx_data7,
           LVDS_TX_lvds_tx_data8    => LVDS_TX_lvds_tx_data8,
           LVDS_RX_clk      => #INSERT_YOUR_CLOCK_NAME,
           LVDS_RX_lvds_rx_data1    => LVDS_RX_lvds_rx_data1,
           LVDS_RX_lvds_rx_data2    => LVDS_RX_lvds_rx_data2,
           LVDS_RX_lvds_rx_data3    => LVDS_RX_lvds_rx_data3,
           LVDS_RX_lvds_rx_data4    => LVDS_RX_lvds_rx_data4,
           LVDS_RX_lvds_rx_data5    => LVDS_RX_lvds_rx_data5,
           LVDS_RX_lvds_rx_data6    => LVDS_RX_lvds_rx_data6,
           LVDS_RX_lvds_rx_data7    => LVDS_RX_lvds_rx_data7,
           LVDS_RX_lvds_rx_data8    => LVDS_RX_lvds_rx_data8,
           LVDS_RX_lvds_rx_data_slip1   => LVDS_RX_lvds_rx_data_slip1,
           LVDS_RX_lvds_rx_data_slip2   => LVDS_RX_lvds_rx_data_slip2,
           LVDS_RX_lvds_rx_data_slip3   => LVDS_RX_lvds_rx_data_slip3,
           LVDS_RX_lvds_rx_data_slip4   => LVDS_RX_lvds_rx_data_slip4,
           LVDS_RX_lvds_rx_data_slip5   => LVDS_RX_lvds_rx_data_slip5,
           LVDS_RX_lvds_rx_data_slip6   => LVDS_RX_lvds_rx_data_slip6,
           LVDS_RX_lvds_rx_data_slip7   => LVDS_RX_lvds_rx_data_slip7,
           LVDS_RX_lvds_rx_data_slip8   => LVDS_RX_lvds_rx_data_slip8,
           LVDS_RX_stat1    => LVDS_RX_stat1,
           LVDS_RX_stat2    => LVDS_RX_stat2,
           LVDS_RX_stat3    => LVDS_RX_stat3,
           LVDS_RX_stat4    => LVDS_RX_stat4,
           LVDS_RX_stat5    => LVDS_RX_stat5,
           LVDS_RX_stat6    => LVDS_RX_stat6,
           LVDS_RX_stat7    => LVDS_RX_stat7,
           LVDS_RX_stat8    => LVDS_RX_stat8,
           vio_ctrl_status_clk => #INSERT_YOUR_CLOCK_NAME,
           vio_ctrl_status_pll_locked => vio_ctrl_status_pll_locked,
           vio_ctrl_status_rx_heartbeat => vio_ctrl_status_rx_heartbeat,
           vio_ctrl_status_tx_heartbeat => vio_ctrl_status_tx_heartbeat,
           vio_ctrl_status_det_pass => vio_ctrl_status_det_pass,
           vio_ctrl_status_stat1 => vio_ctrl_status_stat1,
           vio_ctrl_status_stat2 => vio_ctrl_status_stat2,
           vio_ctrl_status_stat3 => vio_ctrl_status_stat3,
           vio_ctrl_status_stat4 => vio_ctrl_status_stat4,
           vio_ctrl_status_stat5 => vio_ctrl_status_stat5,
           vio_ctrl_status_stat6 => vio_ctrl_status_stat6,
           vio_ctrl_status_stat7 => vio_ctrl_status_stat7,
           vio_ctrl_status_stat8 => vio_ctrl_status_stat8,
           vio_ctrl_status_data_source => vio_ctrl_status_data_source,
           vio_ctrl_status_lvds_tx_data => vio_ctrl_status_lvds_tx_data,
           vio_ctrl_status_err_clear => vio_ctrl_status_err_clear,
           vio_ctrl_status_bitslip_binding => vio_ctrl_status_bitslip_binding,
           vio_ctrl_status_bitslip_all => vio_ctrl_status_bitslip_all,
           vio_ctrl_status_bitslip1 => vio_ctrl_status_bitslip1,
           vio_ctrl_status_bitslip2 => vio_ctrl_status_bitslip2,
           vio_ctrl_status_bitslip3 => vio_ctrl_status_bitslip3,
           vio_ctrl_status_bitslip4 => vio_ctrl_status_bitslip4,
           vio_ctrl_status_bitslip5 => vio_ctrl_status_bitslip5,
           vio_ctrl_status_bitslip6 => vio_ctrl_status_bitslip6,
           vio_ctrl_status_bitslip7 => vio_ctrl_status_bitslip7,
           vio_ctrl_status_bitslip8 => vio_ctrl_status_bitslip8,
           vio_tx_data_clk => #INSERT_YOUR_CLOCK_NAME,
           vio_tx_data_lvds_tx_data1 => vio_tx_data_lvds_tx_data1,
           vio_tx_data_lvds_tx_data2 => vio_tx_data_lvds_tx_data2,
           vio_tx_data_lvds_tx_data3 => vio_tx_data_lvds_tx_data3,
           vio_tx_data_lvds_tx_data4 => vio_tx_data_lvds_tx_data4,
           vio_tx_data_lvds_tx_data5 => vio_tx_data_lvds_tx_data5,
           vio_tx_data_lvds_tx_data6 => vio_tx_data_lvds_tx_data6,
           vio_tx_data_lvds_tx_data7 => vio_tx_data_lvds_tx_data7,
           vio_tx_data_lvds_tx_data8 => vio_tx_data_lvds_tx_data8,
           vio_rx_data_clk => #INSERT_YOUR_CLOCK_NAME,
           vio_rx_data_lvds_rx_data1 => vio_rx_data_lvds_rx_data1,
           vio_rx_data_lvds_rx_data2 => vio_rx_data_lvds_rx_data2,
           vio_rx_data_lvds_rx_data3 => vio_rx_data_lvds_rx_data3,
           vio_rx_data_lvds_rx_data4 => vio_rx_data_lvds_rx_data4,
           vio_rx_data_lvds_rx_data5 => vio_rx_data_lvds_rx_data5,
           vio_rx_data_lvds_rx_data6 => vio_rx_data_lvds_rx_data6,
           vio_rx_data_lvds_rx_data7 => vio_rx_data_lvds_rx_data7,
           vio_rx_data_lvds_rx_data8 => vio_rx_data_lvds_rx_data8,
           vio_rx_data_lvds_rx_data_slip1 => vio_rx_data_lvds_rx_data_slip1,
           vio_rx_data_lvds_rx_data_slip2 => vio_rx_data_lvds_rx_data_slip2,
           vio_rx_data_lvds_rx_data_slip3 => vio_rx_data_lvds_rx_data_slip3,
           vio_rx_data_lvds_rx_data_slip4 => vio_rx_data_lvds_rx_data_slip4,
           vio_rx_data_lvds_rx_data_slip5 => vio_rx_data_lvds_rx_data_slip5,
           vio_rx_data_lvds_rx_data_slip6 => vio_rx_data_lvds_rx_data_slip6,
           vio_rx_data_lvds_rx_data_slip7 => vio_rx_data_lvds_rx_data_slip7,
           vio_rx_data_lvds_rx_data_slip8 => vio_rx_data_lvds_rx_data_slip8,
           vio_rx_data_err_sum1 => vio_rx_data_err_sum1,
           vio_rx_data_err_sum2 => vio_rx_data_err_sum2,
           vio_rx_data_err_sum3 => vio_rx_data_err_sum3,
           vio_rx_data_err_sum4 => vio_rx_data_err_sum4,
           vio_rx_data_err_sum5 => vio_rx_data_err_sum5,
           vio_rx_data_err_sum6 => vio_rx_data_err_sum6,
           vio_rx_data_err_sum7 => vio_rx_data_err_sum7,
           vio_rx_data_err_sum8 => vio_rx_data_err_sum8
         );
------------------------ End INSTANTIATION Template ---------

--------------------------------------------------------------------------------
-- Copyright (C) 2013-2019 Efinix Inc. All rights reserved.              
--
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-- protected by  copyright. All rights  are reserved.  This notice       
-- refers to original work by Efinix, Inc. which may be derivitive       
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-- case of derivative work, nothing in this notice overrides the         
-- original author's license agreement.  Where applicable, the           
-- original license agreement is included in it's original               
-- unmodified form immediately below this header.                        
--                                                                       
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--------------------------------------------------------------------------------
